• DocumentCode
    3336877
  • Title

    Towards totally self-checking delay-insensitive systems

  • Author

    Piestrak, S.J. ; Nanya, T.

  • Author_Institution
    Inst. of Eng. Cybern., Tech. Univ. Wroclaw, Poland
  • fYear
    1995
  • fDate
    27-30 June 1995
  • Firstpage
    228
  • Lastpage
    237
  • Abstract
    Considers designing quasi-delay-insensitive (QDI) combinational circuits (CCs), a class of self-timed (asynchronous) circuits. The necessity of coding both inputs and outputs of any QDI CC by using unordered codes naturally leads to inverter-free realization. The analysis of behavior of a QDI CC with input errors leads to the observation that it is impossible to avoid the so-called late detection problem. The new set of correct definitions of the code-disjoint QDI CC and of the totally self-checking (TSC) QDI CC is introduced. The detailed analysis of the behavior of a faulty QDI system with internal permanent faults shows that: (1) late detection, (2) the possibility of occurrence of invalid transitions, and (3) premature completion, seem to be the inherent properties of any QDI CC, which preclude its fault-secure (hence TSC) implementation for some single stuck-at faults. The first ever self-testing code-disjoint completion checker is proposed. Finally, an extensive study of designing self-testing code-disjoint QDI CCs is presented.<>
  • Keywords
    codes; combinational circuits; delays; encoding; fault diagnosis; logic testing; asynchronous circuits; circuit design; code-disjoint circuit; fault-secure implementation; faulty system behaviour; input coding; input errors; internal permanent faults; invalid transitions; inverter-free realization; late detection problem; output coding; premature completion; quasi-delay-insensitive combinational circuits; self-testing code-disjoint completion checker; self-timed circuits; stuck-at faults; totally self-checking delay-insensitive systems; unordered codes; Built-in self-test; Circuit faults; Clocks; Computer science; Cybernetics; Delay systems; Electrical fault detection; Fault detection; Logic gates; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault-Tolerant Computing, 1995. FTCS-25. Digest of Papers., Twenty-Fifth International Symposium on
  • Conference_Location
    Pasadena, CA, USA
  • Print_ISBN
    0-8186-7079-7
  • Type

    conf

  • DOI
    10.1109/FTCS.1995.466975
  • Filename
    466975