Scaling issues in IDDG FinFET at small gate length

Double gate devices, especially FinFETs have emerged as a superior alternative to conventional bulk MOSFETs to continue scaling down to sub 32 nm regime. According to the specified scaling length, a FinFET structure is superior in controlling short-channel effects (SCEs). Independent control of front and back gate in double gate (DG) devices reduces the effective switching capacitance and, hence, the dynamic power dissipation. In this paper we propose IDDG-FinFET scalable to 10 nm and its parameter analysis.