Title :
A switch-level algorithm for simulation of transients in combinational logic
Author :
Dahlgren, P. ; Liden, P.
Author_Institution :
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
Abstract :
A two-step switch-level algorithm for fault simulation of transients in CMOS networks is presented. The first step models the fault propagation locally from the fault injection site to the subsequent CMOS blocks. It is shown that the pulse width of a transient is a vital parameter in the propagation process. A first-order RC network model for the prediction of the width of transients is used. The second step consists of a set of rules for the propagation of fully developed transients through basic CMOS blocks. The fact that transients may fade out during propagation is efficiently modeled by taking into account their pulse widths. The proposed algorithm shows good agreement with electrical-level simulations in predicting the effects of device-level transients.<>
Keywords :
CMOS integrated circuits; circuit analysis computing; combinational circuits; fault tolerant computing; logic CAD; transients; CMOS blocks; CMOS networks; RC network model; combinational logic; device-level transients; electrical-level simulations; fault injection site; fault propagation; fault simulation; pulse width; resistor-capacitor network; switch-level algorithm; transient width prediction; transients simulation; CMOS logic circuits; Circuit faults; Circuit simulation; Computational modeling; Computer networks; Computer simulation; Intelligent networks; Semiconductor device modeling; Space vector pulse width modulation; Switches;
Conference_Titel :
Fault-Tolerant Computing, 1995. FTCS-25. Digest of Papers., Twenty-Fifth International Symposium on
Conference_Location :
Pasadena, CA, USA
Print_ISBN :
0-8186-7079-7
DOI :
10.1109/FTCS.1995.466977
