Synthesis for testability by sequential redundancy removal using retiming

Author

Yotsuyanagi, H. ; Kajihara, S. ; Kinoshita, K.

Author_Institution

Dept. of Appl. Phys., Osaka Univ., Japan

fYear

1995

fDate

27-30 June 1995

Firstpage

33

Lastpage

40

Abstract

The existence of sequential redundancy degrades testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy is converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. Retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits is enhanced. Experimental results for ISCAS´89 benchmark circuits show the effectiveness of this method for optimizing circuits.<>

Keywords

design for testability; flip-flops; logic testing; redundancy; sequential circuits; timing; ISCAS´89 benchmark circuits; circuit optimisation; combinational redundancy; combinational test generation technique; flip-flop rearrangements; retiming; sequential circuits; sequential redundancy removal; synthesis for testability; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Fault diagnosis; Flip-flops; Logic circuits; Redundancy; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1995. FTCS-25. Digest of Papers., Twenty-Fifth International Symposium on

Conference_Location

Pasadena, CA, USA

Print_ISBN

0-8186-7079-7

Type

conf

DOI

10.1109/FTCS.1995.466981

Filename

466981