Noise and delay uncertainty studies for coupled RC interconnects

The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of SPICE for an arbitrary ramp input. We also develop a simplified delay model for estimating delays on coupled RC lines considering input slew times for both agressor and victim lines. We then apply our model along with SPICE simulation to perform various studies of delay uncertainty in coupled interconnects. With respect to the effects of changing aggressor slew time on victim delay (i.e., delay variation), we observe that the victim delay is worst when the aggressor is switching very fast (e.g., step input). For local interconnects the delay variation (change in victim delay with varying input slew) can be as high as 70%. On the other hand, delay variation is around 10% for global interconnects. We also observe that the difference between minimum and maximum delay (i.e., delay uncertainty) decreases significantly as slew times are increased. Delay uncertainty on the victim wire is high for global wires as compared to local wires, a consequence of differing ratios of coupling to parallel-plate capacitance, and wire to load capacitance. We believe that our noise and delay analytical models form an effective basis for methodologies that lead to less over-design and guard-banding in high-performance system designs