DocumentCode
3338048
Title
Performance enhancement through optimal n-tier multilevel interconnect architectures
Author
Venkatesan, R. ; Davis, Jcffrcy A. ; Meindl, James D.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
fYear
1999
fDate
1999
Firstpage
19
Lastpage
23
Abstract
A stochastic wire-length distribution is used to develop an optimal n-tier multilevel interconnect architecture for a 0.1 μm ASIC macrocell. The results of the n-tier design when compared to the 2-tier design show a 30% reduction of metal levels, three fold reduction in macrocell area or three fold increase in clock frequency
Keywords
VLSI; application specific integrated circuits; cellular arrays; circuit optimisation; integrated circuit design; integrated circuit interconnections; logic CAD; logic arrays; wiring; 0.1 micron; ASIC macrocell; clock frequency; macrocell area; metal levels; optimal n-tier multilevel interconnect architectures; stochastic wire-length distribution; Application specific integrated circuits; Clocks; Delay effects; Frequency; Logic arrays; Logic design; Logic gates; Macrocell networks; Stochastic processes; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806465
Filename
806465
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