Target processor and co-verification environment independent adapter-a technology to shorten cycle-time for retargeting TI processor simulators in HW/SW co-verification environments

Hardware-software co-verification is essential for design and verification of embedded systems at the early development stages to reduce development cycle time. A number of co-verification environments are available from EDA vendors to simulate such designs, each with its own interfaces and mechanisms. TI provides co-verification models for its DSP devices and cDSP megamodules in these environments. We present an approach that enables TI´s instruction set simulators to seamlessly be integrated in these environments. This hides the EDA environment specific interfaces from the simulator/model developer thereby shortening the co-verification model development cycle times