Methodology for ATM-cell processing system design

ATM (asynchronous transfer mode) has been considered by the telecommunication industry to be the ultimate solution to the networking requirements of broadband communication. We discuss the implementation of an ATM cell processing system that provides guaranteed quality of service (QoS) for a broad range of services by per-connection maintenance. The complexity in this application domain is based on the implementation and the verification of complex hierarchical control structures. To overcome this problem, we propose a design methodology, which is three-fold. First we use abstract executable specifications in C++ for functional verification, second we introduce a design for verification (DfV) strategy to reduce the number of test cases and third to increase modeling efficiency, we have chosen behavioral VHDL modeling and high-level behavioral synthesis for the applicable parts of the design. In this paper we present the area overhead introduced due to our methodology compared to the advantage in terms of reducing the verification effort