System exploration and synthesis from SDL of an ATM switch component

We describe the complete hardware synthesis of an ATM switch component, characterized by concurrent and dynamic processes, very high bit-rate data streams, and intensive data storage and transfer. The methodology used to synthesize it bridges the gap between an SDL system specification and an optimized single-chip implementation of communicating hardware processors, that satisfies stringent constraints on area, performance, and power. The novelty of this methodology is that through stepwise exploration, and gradual incorporation of timing constraints, it supports new optimization methods in view of memory and concurrency management, and expensive late iterations are avoided