Testability synthesis for jumping carry adder

Author

Wagh, Mahesh ; Chen, Chzen-In Ilenry

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

1999

fDate

1999

Firstpage

130

Lastpage

134

Abstract

Synthesis for testability process ensures that the design is testable, which exploits the fundamental relationships between don´t care and redundancy in combinational and sequential circuits. In this paper a testability synthesis with redundancy removal for designing high speed jumping carry adders is presented. The 1.2 μm CMOS realization of the 32-bit testable adder performs the addition operation in 4.09 ns. Removal of redundant logic yields a 100% testable design with significant improvement in performance. A 15% improvement in speed and a 25% reduction in overall area has been observed when compared with the untestable design

Keywords

CMOS logic circuits; adders; carry logic; circuit CAD; design for testability; high level synthesis; high-speed integrated circuits; integrated circuit design; integrated circuit testing; logic testing; redundancy; 1.2 micron; 32 bit; 4.09 ns; ATPG; CMOS realization; DFT; HLS; high speed adders; jumping carry adder; redundancy removal; redundant logic removal; testability synthesis; testable design; Adders; CMOS logic circuits; Multiplexing; Sequential analysis; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806490

Filename

806490