Title :
An evolutionary 3D over-the-cell router
Author :
Goni, B.M. ; Arslan, T.
Author_Institution :
Edinburgh Univ., UK
Abstract :
This paper reports on a new algorithm which carries out combined 3D (4-layer) and over-the-cell (OTC) routing in order to reduce chip area in 3D VLSI technology. In order to cope with the complexity of the search space, the algorithm is tailored around a class of heuristic techniques called genetic algorithms. Our results indicate up to 62% savings in chip area when compared to conventional multilayer channel routers, using several internationally well known benchmarks
Keywords :
VLSI; circuit layout CAD; genetic algorithms; integrated circuit layout; network routing; 3D VLSI technology; 4-layer routing; chip area reduction; evolutionary 3D over-the-cell router; genetic algorithm; heuristic techniques; over-the-cell routing; Costs; Delay; Genetic algorithms; Nonhomogeneous media; Partitioning algorithms; Routing; Silicon on insulator technology; Space technology; Tiles; Very large scale integration;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806505
