Efficient generation of timing and power polynomial models from lookup tables for SoC designs

A new scheme is presented for generating optimal timing and power models, which can speed up timing and power analyses with full accuracy in system-on-chip (SoC) designs. In this scheme, the nonlinear multidimensional timing and power lookup tables in semiconductor libraries are transformed into optimized (piecewise) polynomial equations in an efficient and accurate manner. The transform problem is mathematically defined as a least square problem, which is efficiently solved by a set of robust numerical algorithms. These optimized polynomial equations are then represented using the delay and power calculation language (DPCL), which can be complied into object code and used by various EDA tools