Title :
Test ready core design for a DSP core
Author_Institution :
Design Service Team, Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
In this paper, test ready core design techniques for SSP1820, a hard core compatible with the OakDSPCore, are presented. The basic strategy is to implement a serial test access structure with test isolation capability around the hard core so that the pre-developed functional test vectors can be applied serially. To provide multiple integration choices, two serial test access schemes of JTAG and isolation rings with different number of scan chains are considered. Compared to the original core, the test ready cores implemented offer the advantage of test access and test isolation with less pin overhead. Especially, several integration choices available for the core can enable efficient core test integration to meet various design-specific test requirements
Keywords :
boundary scan testing; digital signal processing chips; integrated circuit design; integrated circuit testing; logic design; logic testing; timing; DSP core; JTAG; OakDSPCore compatibility; SSP1820; core test integration; functional test vectors; isolation rings; pin overhead reduction; scan chains; serial test access structure; test isolation capability; test ready core design techniques; Application specific integrated circuits; Automatic test pattern generation; Chip scale packaging; Cities and towns; Digital signal processing; Large scale integration; Logic testing; Pins; System testing; System-on-a-chip;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806513
