Global interconnect design for high speed ULSI and system-on-package

In this paper, interconnects are treated as important design objects for high performance ASICs in deep submicron technology. Their electrical performance and optimal layout schemes are studied with regards to the interconnect delay and signal integrity issues. The maximum usable interconnect length for signal integrity is defined and referred to as the design guidelines. The study emphasizes high speed ULSI on-chip global bus and off-chip interconnects for system-on-package-an attractive system integration route before system-on-chip. The models and design guidelines developed from this paper is useful for a rule-based interconnect model as well as for building a parameterized dynamic interconnect library in advanced ASIC designs