Design of ultra low power pseudo-asynchronous SRAM

This paper describes the design of a low-power, 0.9 V, 1.2 nsec, multi-port, pseudo-asynchronous SRAM which consists of a single READ-bit-line and a single WRITE-bit-line per port. This SRAM employs a new memory cell with a feedback self-timed wave-pipeline architecture technique to increase speed and reduce power dissipation. Each SRAM cell contains a preset transistor which sets the content of a memory word to all `1´s prior to a write access. This allows all actual writes to be done by writing `0´ to the appropriated bits. Also each SRAM cell has a pull-down transistor as a buffer which discharges precharged bit line to read a `0´. Thus, a memory write requires only a single write bit-line and a single read bit-line