Design of ultra low power pseudo-asynchronous SRAM

Author

Lee, Hyun

Author_Institution

Lucent Technol., Allentown, PA, USA

fYear

1999

fDate

1999

Firstpage

275

Abstract

This paper describes the design of a low-power, 0.9 V, 1.2 nsec, multi-port, pseudo-asynchronous SRAM which consists of a single READ-bit-line and a single WRITE-bit-line per port. This SRAM employs a new memory cell with a feedback self-timed wave-pipeline architecture technique to increase speed and reduce power dissipation. Each SRAM cell contains a preset transistor which sets the content of a memory word to all `1´s prior to a write access. This allows all actual writes to be done by writing `0´ to the appropriated bits. Also each SRAM cell has a pull-down transistor as a buffer which discharges precharged bit line to read a `0´. Thus, a memory write requires only a single write bit-line and a single read bit-line

Keywords

SRAM chips; asynchronous circuits; high-speed integrated circuits; integrated circuit design; low-power electronics; multiport networks; parallel memories; pipeline processing; 0.9 V; 1.2 ns; feedback self-timed wave-pipeline architecture technique; memory cell; multiport pseudo-asynchronous SRAM; power dissipation; preset transistor; pull-down transistor; single read-bit-line; single write-bit-line; ultra low power pseudo-asynchronous SRAM design; Asynchronous circuits; Delay effects; Digital signal processing; Leakage current; Memory management; Power dissipation; Power supplies; Random access memory; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806518

Filename

806518