Title :
Low power parallel multiplier design for DSP applications through coefficient optimization
Author :
Hong, Sangjin ; Kim, Suhwan ; Papaefthymiou, Marios C. ; Stark, Wayne E.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication´s outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers
Keywords :
circuit optimisation; critical path analysis; digital signal processing chips; fast Fourier transforms; logic partitioning; logic simulation; low-power electronics; multiplying circuits; parallel architectures; DSP; coefficient multiplications; coefficient optimization; critical paths; digital signal processing; energy savings; fast Fourier transform; low power parallel multiplier design; multiplier design methodology; partitioning; quantization error; scaled supply voltage; simulation results; throughput; very low power dissipation; Application software; Computational modeling; Design methodology; Design optimization; Digital signal processing; Fast Fourier transforms; Power dissipation; Quantization; Throughput; Voltage;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806521