DocumentCode
3339083
Title
Second generation programmable artificial retina
Author
Paillet, Fabrice ; Mercier, Darnien ; Bernard, Thierry M.
Author_Institution
CTA/GIP, Arcueil, France
fYear
1999
fDate
1999
Firstpage
304
Lastpage
309
Abstract
Lodging a general enough digital processing element (PE) in each pixel of a CMOS imager aims at getting a programmable artificial retina (PAR) that can support fast, compact, low power and low cost vision. Using original architecture and circuit techniques, we have designed and operated a 128×128 PAR capable of grey-level image processing and pattern recognition with not even 50 transistors per PE
Keywords
CMOS image sensors; computer vision; digital signal processing chips; image recognition; integrated circuit design; 0.8 mum; 128 pixel; 16384 pixel; CMOS imager; architecture techniques; circuit techniques; compact low power low cost vision; digital processing element; grey-level image processing; pattern recognition; second generation programmable artificial retina; CMOS process; CMOS technology; Charge coupled devices; Circuits; Costs; Image processing; Optical arrays; Pixel; Retina; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806524
Filename
806524
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