DocumentCode
3339193
Title
A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing
Author
Hardt, W. ; Kleinjohann, B. ; Rettberg, A. ; Kleinjohann, E.
Author_Institution
Paderborn Univ., Germany
fYear
1999
fDate
1999
Firstpage
336
Lastpage
339
Abstract
In this paper we present the architecture and implementation of our new configurable and scalable chip well suited for rapid prototyping of asynchronous designs. A flexible number of arithmetic operators, e.g. 720 add/sub operators for the first chip, are interconnected via a configurable network. For demonstration a DCT algorithm was mapped onto the chip
Keywords
asynchronous circuits; discrete cosine transforms; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; logic design; pipeline arithmetic; rapid prototyping (industrial); reconfigurable architectures; signal processing; DCT algorithm; FLYSIG prototyping approach; FPGAs; add/sub operator interconnection; arithmetic operators; asynchronous designs; bit-serial pipelining; configurable network; configurable scalable architecture; rapid prototyping; signal processing; Clocks; Delay; Design methodology; Field programmable gate arrays; Libraries; Logic design; Protocols; Prototypes; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806530
Filename
806530
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