Title :
A novel high-performance low-power CMOS master-slave flip-flop
Author :
Hsu, Steven ; Lu, Shih-Lien
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
Abstract :
A novel high-performance low-power CMOS master-slave flip-flop is proposed. The proposed flip-flop consumes very low power, while having a very small clock load and data load. In our HSPICE simulations, the new flip-flop has an optimal power-delay product better than previous master-slave structures. The proposed flip-flop is compared to other reported master-slave flip-flops
Keywords :
CMOS logic circuits; SPICE; flip-flops; logic simulation; low-power electronics; threshold logic; HSPICE simulations; complementary pass logic; high-performance low-power CMOS master-slave flip-flop; multi-threshold techniques; optimal power-delay product; very low power consumption; very small clock load; very small data load; CMOS logic circuits; Capacitance; Clocks; Digital systems; Energy consumption; Equations; Flip-flops; Latches; Master-slave; Power dissipation;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806531
