DocumentCode
3339611
Title
Tutorial on interconnect modeling, signal integrity and reliability verification in deep sub-micron digital designs
Author
Nagaraj, N.S. ; Balsara, Poras ; Cantrell, Cyrus
Author_Institution
Texas Instruments Inc.
fYear
1999
fDate
18-18 Sept. 1999
Firstpage
421
Lastpage
421
Keywords
Delay; Electronics industry; Instruments; Integrated circuit interconnections; LAN interconnection; Semiconductor device noise; Signal analysis; Signal design; Tutorial; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806548
Filename
806548
Link To Document