An on-chip fast readout sparsification for a 256-pixel 3D device

A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of 256 pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect fate-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic shares one layer of double-layer design that will be stacked at the end of the fabrication process.