Title :
Loop filter design considerations for clock and data recovery circuits [PLL]
Author :
Ou, Jack ; Caggiano, M.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Abstract :
This paper describes a detailed 3rd order analysis that accounts for charge pump output resistance, bandwidth controlling resistor, damping capacitor and ripple capacitor as well as other important PLL parameters such as Kd, the phase detector gain and KVCO, the VCO gain. Equations derived in this paper can be implemented in commercial software programs such as MATLAB to generate behavior models.
Keywords :
filters; network analysis; phase detectors; phase locked loops; synchronisation; voltage-controlled oscillators; PLL parameters; VCO gain; bandwidth controlling resistor; behavior models; charge pump output resistance; clock recovery circuits; damping capacitor; data recovery circuits; loop filter design; phase detector gain; phase locked loop; ripple capacitor; Bandwidth; Capacitors; Charge pumps; Circuits; Clocks; Damping; Filters; Phase locked loops; Resistors; Voltage-controlled oscillators;
Conference_Titel :
Mixed-Signal Design, 2003. Southwest Symposium on
Print_ISBN :
0-7803-7778-8
DOI :
10.1109/SSMSD.2003.1190401
