Fast Control and Timing distribution based on FPGA-embedded serial Transceivers

The Fast Control and Timing distribution System (FCTS) of a High Energy Physics experiment must distribute the clock with minimum jitter and it must transfer data with a fixed latency. In fact, transferred data include trigger signals (accept/reject and qualifiers) and fast control commands, whose timing must be preserved. Latest Field Programmable Gate Arrays (FPGAs) offer embedded high-speed Serializers-Deserializers (SerDes), which can be exploited to implement serial links for FCTS applications. In this work, we present jitter measurements on a link for FCTS fully based on FPGA-embedded SerDes. Data and clock are recovered with a fixed latency even after a power cycle or a loss of lock. We implemented our architecture with a Xilinx GTP Transceiver embedded in Virtex 5 FPGAs. We performed tests at 2.5 Gb/s and we distributed a clock running at 62.5 MHz. Our link has been tested with the 8b10b encoding, a wide-spread standard, and the scrambling method adopted by the GigaBit Transceiver project under development at CERN. We present our test results in terms of jitter performance on the recovered clock both in the time and in the frequency domain (i.e. phase noise spectrum measurements). We also present and discuss the benefit of an external jitter cleaner to reduce the phase noise on the recovered clock.