Title :
A compact phase interpolator for 3.125G Serdes application
Author :
Jiang, Yueming ; Piovaccari, A.
Author_Institution :
Cadence Design Syst. Inc., Cary, NC, USA
Abstract :
This paper describes an area-efficient, low-voltage, low-power phase interpolator for clock recovery in a 3.125/2.5 Gbps dual mode serial link application. It has been implemented in both 0.15 μm and 0.13 μm digital CMOS processes. It occupies 0.02 mm2 and dissipates less than 10 mW in both processes. The measurement results from the 0.13 μm transceiver show a BER<10-14 with the presence of ±200 ppm frequency offset and 0.65 UIp-p combined deterministic, random and sinusoidal jitter.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; data communication equipment; digital communication; error statistics; high-speed integrated circuits; interpolation; synchronisation; 0.13 micron; 0.15 micron; 10 mW; 2.5 Gbit/s; 3.125 Gbit/s; 3.125G Serdes application; BER; CMOS ASIC; area-efficient interpolator; bit error rate; clock recovery; compact phase interpolator; digital CMOS processes; dual mode serial link application; low-power interpolator; low-voltage interpolator; Bit error rate; Clocks; Data communication; Detectors; Frequency; Jitter; Phase detection; Phase locked loops; System-on-a-chip; Timing;
Conference_Titel :
Mixed-Signal Design, 2003. Southwest Symposium on
Print_ISBN :
0-7803-7778-8
DOI :
10.1109/SSMSD.2003.1190436
