A novel high speed automatic layout system to place and route test structures for parametric test capability

In this paper, we created a generalized framework for the automated placement and routing of analog test structures. We exploited the concept of terminal properties when placing and routing the test structures and generated a library of place and routing strategies for different architectures. This new approach significantly reduces layout time, maximizes the reuse of place and route routines, and facilitates the introduction of a holistic parametric test design flow.