A test structure for channel length engineering of NAND gates in standard cell library

A channel length engineering technique for optimization of primitive cells in standard cell libraries is proposed and a test structure to analyze the operation performance and leakage current of 3-input NAND is presented. Since the topmost transistor (Nl) in the three series connected n-MOSFETs of 3-input NAND has the largest VDS, subthreshold leakage current can be reduced by optimizing a channel length L of Nl. The leakage current of NANDs for input vector of (0, 1, 1) decreases by about 22 ~ 40 % with the change of L (Nl) from 0.1 to 0.11 mum. The channel length engineering of series connected MOSFETs provides a leakage reduction method for standard cells without significant increase of delay time, maintaining the same cell size.