• DocumentCode
    3340709
  • Title

    Test structures for the evaluation of 3D chip interconnection schemes

  • Author

    Mathewson, A. ; Brun, J. ; Franiatte, R. ; Nowodzinski, A. ; Ancient, R. ; Sillon, N. ; Depoutot, F. ; Dubois-Bonvalot, B.

  • fYear
    2008
  • fDate
    24-27 March 2008
  • Firstpage
    117
  • Lastpage
    122
  • Abstract
    In this paper a test structure is described which facilitates the evaluation of interconnection schemes for chip on wafer attachment and interconnection. Microinsert technology is described and some of the characterization that the test structure permits is discussed. Thermal cycling experiments were performed on this test structure and although the resistance of the contact chain seemed not to change as a function of number of cycles, detailed investigation revealed that the metal resistance was reducing while contact resistance was increasing and the two effects were trading off against each other. Possible explanations for this behavior have been provided.
  • Keywords
    integrated circuit interconnections; integrated circuit testing; 3D chip interconnection; contact resistance; metal resistance; microinsert technology; test structure; thermal cycling; wafer attachment; wafer interconnection; Microelectronics; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on
  • Conference_Location
    Edinburgh
  • Print_ISBN
    978-1-4244-1800-8
  • Electronic_ISBN
    978-1-4244-1801-5
  • Type

    conf

  • DOI
    10.1109/ICMTS.2008.4509325
  • Filename
    4509325