Fully considered layout variation analysis and compact modeling of MOSFETs and its application to circuit simulation

Author

Tanaka, Takuji ; Satoh, Akira ; Yamaji, Mitsuru ; Yamasaki, Osamu ; Suzuki, Hiroshi ; Sakata, Tsuyoshi ; Inoue, Yoshio ; Ito, Masaru ; Yamaguchi, Seiichiro ; Arimoto, Hiroshi

Author_Institution

FUJITSU Ltd., Akiruno

fYear

2008

fDate

24-27 March 2008

Firstpage

223

Lastpage

227

Abstract

We have developed a total system of circuit design to treat dependency of MOSFET electric characteristics on layout patterns. Our new methodology with two-step multivariate analysis realizes highly reliable compact modeling, and its application to SPICE simulation significantly improves accuracy of circuit modeling. Our system is a powerful tool of design for manufacturing in 65 nm technology node and beyond.

Keywords

MOSFET; SPICE; circuit simulation; digital simulation; electric properties; integrated circuit layout; MOSFET electric characteristics; SPICE simulation; circuit design; circuit modeling; circuit simulation; compact modeling; layout variation analysis; multivariate analysis; Circuit simulation; Circuit synthesis; Circuit testing; Costs; Electric variables; Lithography; MOSFETs; Manufacturing; Power system modeling; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on

Conference_Location

Edinburgh

Print_ISBN

978-1-4244-1800-8

Electronic_ISBN

978-1-4244-1801-5

Type

conf

DOI

10.1109/ICMTS.2008.4509342

Filename

4509342