DocumentCode :
3341175
Title :
Design methodology of CMOS low power
Author :
Dongyan, Hao ; Ming, Zhang ; Wei, Zheng
Author_Institution :
Coll. of Inf. Sci., Zhejiang Univ., Hangzhou
fYear :
2005
fDate :
14-17 Dec. 2005
Firstpage :
114
Lastpage :
118
Abstract :
The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the IC design industry. In this article, according the design flow of VLSI, we present a survey of low power design methodology at five levels such as system, behavioral, architectural, logic and physical levels
Keywords :
CMOS integrated circuits; VLSI; integrated circuit design; power consumption; CMOS low power; IC design industry; VLSI; low power design methodology; portable electronic devices; power consumption; CMOS logic circuits; Design methodology; Electronics industry; Energy consumption; Energy management; Power dissipation; Power system management; Switching circuits; Threshold voltage; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Technology, 2005. ICIT 2005. IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
0-7803-9484-4
Type :
conf
DOI :
10.1109/ICIT.2005.1600620
Filename :
1600620
Link To Document :
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