Title :
Low-power multiplier design using delayed evaluation
Author :
Sobelman, Gerald E. ; Raatz, Donovan L.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
30 Apr-3 May 1995
Abstract :
A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stablized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier
Keywords :
CMOS logic circuits; delays; digital arithmetic; logic design; multiplying circuits; parallel processing; timing; carry-propagate adder; carry-save adder; circuit design technique; delayed evaluation; dynamic CMOS circuits; low power parallel multipliers; multiplier design; power dissipation characteristics; self-timed evaluate signal; Adders; Capacitance; Circuits; Clocks; Delay; Digital signal processing; Equations; Power dissipation; Power supplies; Voltage;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.523705
