DocumentCode
3341450
Title
An analytic method to calculate emitter follower delay using trial functions in coupled node equations
Author
Brauer, E.J. ; Kang, S.M.
Author_Institution
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Volume
3
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
1580
Abstract
We use a quasi-linear large-signal bipolar junction transistor model and node waveform trial functions in coupled node equations to calculate delay of emitter followers driving fan-out gates and interconnect resistance and capacitance
Keywords
bipolar integrated circuits; bipolar transistors; buffer circuits; delays; equivalent circuits; integrated circuit design; integrated circuit modelling; semiconductor device models; analytic method; bipolar junction transistor model; coupled node equations; emitter follower delay calculation; fan-out gates driving; interconnect capacitance; interconnect resistance; node waveform trial functions; quasi-linear large-signal BJT model; Capacitance; Coupling circuits; Delay estimation; Differential equations; Diodes; Impedance; Integrated circuit interconnections; Steady-state; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.523709
Filename
523709
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