DocumentCode :
3342302
Title :
Retiming for BIST-sequential circuits
Author :
Lejmi, Samir ; Kaminska, Bozena ; Ayari, Bechir
Author_Institution :
Ecole Polytech. de Montreal, Que., Canada
Volume :
3
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
1740
Abstract :
Pseudoexhaustive BIST of sequential circuits consists of breaking all cycles in the circuit, partitioning the obtained acyclic circuit by placing some segmentation cells in the circuit, and balancing the partitioned circuit by introducing (or selecting in the scan path) additional flip-flops as delays in order to apply combinational TPG methods, In this paper, we present a new efficient method for pseudoexhaustive BIST. We first determine the flip-flops that cause the unbalanced structure of the acyclic circuit by using the peripheral retiming and, second, we use these flip-flops for the circuit partitioning. Thus, these flip-flops can be used for both partitioning and balancing problem of the circuit at the same time. We propose an algorithm for a partitioning problem which combines our idea with existing approaches
Keywords :
built-in self test; delays; flip-flops; logic partitioning; logic testing; sequential circuits; timing; BIST-sequential circuits; acyclic circuit; balancing problem; circuit partitioning; delays; flip-flops; partitioned circuit; peripheral retiming; pseudoexhaustive BIST; scan path; segmentation cells; unbalanced structure; Built-in self-test; Circuit testing; Combinational circuits; Costs; Delay; Flip-flops; Hardware; Registers; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.523749
Filename :
523749
Link To Document :
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