PLATO P: PLA timing optimization by partitioning

Author

Liu, Shihming ; Pedram, Massoud ; Despain, Alvin M.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

3

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

1744

Abstract

This paper addresses the problem of partitioning a large PLA into a number of smaller PLA´s (sub-PLA´s) such that the total area of these sub-PLA´s is minimum and the cycle time of the partitioned circuit is minimized. First, we describe an iterative improvement method that deals with the case that sub-PLA´s assume arbitrary sizes. Second, we present a partitioning technique based on fuzzy logic that deals with the case that the sizes of the sub-PLA´s are fixed. Finally, we describe a method that considers not only delay through each sub-PLA, but also loading of sub-PLA´s on the stage that is driving them. These techniques have been implemented and significantly outperformed conventional PLA partitioning schemes

Keywords

VLSI; circuit optimisation; delays; fuzzy logic; iterative methods; logic CAD; logic partitioning; programmable logic arrays; timing; IC design; PLA; PLATO P; VLSI; cycle time; delay; fuzzy logic; iterative improvement method; logic design; partitioning; timing optimization; CMOS technology; Circuits; Delay; Fuzzy logic; Iterative methods; Logic arrays; Logic design; Programmable logic arrays; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-2570-2

Type

conf

DOI

10.1109/ISCAS.1995.523750

Filename

523750