• DocumentCode
    3343124
  • Title

    Mixed deterministic and pseudorandom test vector generator based on cellular automata structures

  • Author

    Boubezari, Samir ; Kaminska, Bozena

  • Author_Institution
    Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
  • Volume
    3
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    1928
  • Abstract
    This paper proposes a new approach for designing a cost-effective on-chip Built-in Self-Test (BIST) generator through the use of Cellular Automata (CA) structures. The BIST generator thus designed is used to generate pseudorandom as well as deterministic test vectors. It is shown that no complex control logic is required to obtain either sequence. In addition, the resulting Test Vector Generator (TVG) is very efficient in terms of speed performances and is very regular and testable. Simulation of various benchmark circuits has given good results in terms of hardware size and test application time
  • Keywords
    built-in self test; cellular automata; digital integrated circuits; integrated circuit testing; logic design; logic testing; built-in self-test generator; cellular automata structures; deterministic test vectors; mixed deterministic/pseudorandom technique; onchip BIST generator; pseudorandom test vectors; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Content addressable storage; Design engineering; Hardware; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-2570-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.1995.523796
  • Filename
    523796