DocumentCode
3343542
Title
Distributed diagnostic fault simulation for synchronous sequential circuits by dynamic fault partitioning
Author
Jou, Jer Min ; Chen, Shung-Chih
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
3
fYear
1995
fDate
30 Apr-3 May 1995
Firstpage
2004
Abstract
In this paper, a distributed diagnostic fault simulation for sequential circuits by dynamic fault partitioning is proposed, in which the indistinguishable faults for all the detectable faults are obtained from different machines. Several ISCAS89 benchmark circuits have been experimented on. For a circuit s35932, less than one hour of CPU time is spent by using 4 SUN SPARC stations II
Keywords
circuit analysis computing; fault diagnosis; logic testing; sequential circuits; ISCAS89 benchmark circuits; distributed diagnostic fault simulation; dynamic fault partitioning; logic testing; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Discrete event simulation; Ethernet networks; Fault detection; Sequential circuits; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
0-7803-2570-2
Type
conf
DOI
10.1109/ISCAS.1995.523815
Filename
523815
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