DocumentCode :
3343799
Title :
Detecting errors in digital communications with CRC codes implemented with FPGA
Author :
Anton, C. ; Ionescu, L. ; Tutanescu, I. ; Mazare, A. ; Serban, G.
Author_Institution :
Univ. of Pitesti, Pitesti, Romania
fYear :
2009
fDate :
9-12 Nov. 2009
Firstpage :
1
Lastpage :
6
Abstract :
Generally speaking, cyclic redundancy checks (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied to data storage devices, such as a disk drive. They also have been turned to verify the integrity of files in a system in order to prevent tampering and suggested as a possible algorithm for manipulation detection codes. It has been known that a CRC will not detect all errors but with random noise it is unlikely. In this paper, we present an efficient algorithm for parallel computation of the CRC in data transmission.
Keywords :
cyclic redundancy check codes; field programmable gate arrays; CRC codes; FPGA; cyclic redundancy checks; data storage devices; detecting errors; digital communications; manipulation detection codes; Clocks; Cyclic redundancy check; Cyclic redundancy check codes; Data communication; Digital communication; Field programmable gate arrays; Hardware; Memory; Polynomials; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Internet Technology and Secured Transactions, 2009. ICITST 2009. International Conference for
Conference_Location :
London
Print_ISBN :
978-1-4244-5647-5
Type :
conf
DOI :
10.1109/ICITST.2009.5402630
Filename :
5402630
Link To Document :
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