• DocumentCode
    3344096
  • Title

    A self-test approach using accumulators as test pattern generators

  • Author

    Stroele, Albrecht P.

  • Author_Institution
    Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
  • Volume
    3
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    2120
  • Abstract
    Configurations of adders and registers, which are available in many datapaths, can be utilized to generate patterns and to compact test responses. This paper analyzes the pattern sequences produced by different types of accumulators and shows that they can achieve similar fault coverage as pseudo-random patterns. Compared to the well-known self-test methods that insert test registers, the approach using accumulators saves the additional gates that are needed to implement test registers, and it avoids performance degradation due to additional delays
  • Keywords
    adders; automatic testing; built-in self test; delays; fault diagnosis; integrated circuit testing; logic testing; BIST; adders; datapaths; delays; fault coverage; pattern sequences; performance degradation; pseudo-random patterns; registers; self-test approach; test pattern generators; test responses; Adders; Automatic testing; Built-in self-test; Character generation; Circuit faults; Circuit testing; Fault tolerance; Logic testing; Registers; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-2570-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.1995.523844
  • Filename
    523844