Maximum likelihood carrier phase synchronization in FPGA-based software defined radios

Author

Rice, Michael ; Dick, Chris ; Harris, Fred

Author_Institution

Brigham Young Univ., Provo, UT, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

889

Abstract

Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibility required by modern software defined radios (SDRs), this task must either be performed in a DSP processor (reconfigurable software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization

Keywords

digital radio; field programmable gate arrays; quadrature amplitude modulation; quadrature phase shift keying; radio receivers; signal processing; software architecture; synchronisation; DSP; FPGA-based design; FPGA-based software defined radios; QAM; QPSK; all-digital sampled data receiver; digital signal processing; maximum likelihood carrier phase synchronization; reconfigurable hardware; reconfigurable software; Detectors; Digital signal processing; Field programmable gate arrays; Frequency synchronization; Hardware; Phase detection; Phase locked loops; Quadrature amplitude modulation; Quadrature phase shift keying; Software radio;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941058

Filename

941058