Parameterised floating-point arithmetic on FPGAs

This paper describes the parameterisation, implementation and evaluation of floating-point adders and multipliers for FPGAs. We have developed a method, based on the Handel-C language, for producing technology-independent pipelined designs that allow compile-time parameterisation of design precision and range, and optional inclusion of features such as overflow protection, gradual underflow and rounding modes of the IEEE floating-point format. The resulting designs, when implemented in a Xilinx XCV1000 device, achieve 28 MFLOPs with IEEE single precision floating-point numbers. These designs are used in an optimised implementation for computing the two-dimensional fast Hartley transform. Preliminary results suggest that our implementation is faster than many programmable DSP processors and supercomputers