Design optimization of main-profile MPEG-2 AAC decoder

A system architecture optimized for the 2-channel main-profile MPEG-2 AAC decoder is presented. In order to enable an efficient job scheduling and allocation, the presented system comprises three hardware modules: Huffman decoder module, predictor module, and processing core module which is programmable using an assembly language of its own. The Huffman decoder is designed to finish the requested job in only 1 clock cycle time and the predictor forms parallel processing with other modules, so that utilization of the system resource is maximized. The developed system has been coded in VHDL and the MPEG-2 AAC decoding algorithm is programmed using the assembly language of the processing core. For the verification of the decoding algorithm, the 16-bit PCM output of the system was compared with the result of the floating-point simulation, and the result showed the maximum of 2-bit difference. Functional simulation verified that the developed system can decode standard MPEG-2 AAC main-profile bitstreams in real-time with high accuracy