Title :
Hardware provisions for extended precision floating-point arithmetic
Abstract :
A mode of implementation of the basic floating-point operations of multiplication and addition (subtraction) is discussed which permits the execution of multiple precision floating-point arithmetic with the aid of a single algorithm for multiple precision addition. Speed cannot compete with explicit implementations in hardware but the time consuming overhead of most software implementations is avoided to advantage.
Keywords :
floating point arithmetic; addition; extended precision floating point arithmetic; hardware provisions; multiple precision floating point arithmetic; multiplication; time consuming overhead; Bibliographies; Hardware; Memory management; NASA; Registers; Software; Software algorithms;
Conference_Titel :
Computer Arithmetic (ARITH), 1972 IEEE 2nd Symposium on
Conference_Location :
New York, NY
DOI :
10.1109/ARITH.1972.6153917
