A low-power programmable DSP core architecture for 3G mobile terminals

Author

Kumura, Takahiro ; Ishii, Daiji ; Ikekawa, Masao ; Kuroda, Ichiro ; Yoshida, Makoto

Volume

2

fYear

2001

fDate

2001

Firstpage

1017

Abstract

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications at 384 k bit/sec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks

Keywords

digital arithmetic; digital signal processing chips; instruction sets; land mobile radio; parallel architectures; programmable circuits; speech codecs; video codecs; 384 kbit/s; 3G mobile terminals; 3G wireless communications; 50 mW; DSP instruction set; LMS adaptive filter; VLIW; dual-multiply-accumulate architecture; general-purpose digital signal processor core; low power dissipation; low-power programmable DSP core architecture; power consumption; speech codec; third-generation mobile terminals; very long instruction word; video codec; Communication standards; Digital signal processing; Large scale integration; MPEG 4 Standard; Mobile communication; Modems; National electric code; Power dissipation; Signal processing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on

Conference_Location

Salt Lake City, UT

ISSN

1520-6149

Print_ISBN

0-7803-7041-4

Type

conf

DOI

10.1109/ICASSP.2001.941090

Filename

941090