• DocumentCode
    3345119
  • Title

    MiAMI: Multi-core Aware Processor Affinity for TCP/IP over Multiple Network Interfaces

  • Author

    Jang, Hye-Churn ; Jin, Hyun-Wook

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Konkuk Univ., Seoul, South Korea
  • fYear
    2009
  • fDate
    25-27 Aug. 2009
  • Firstpage
    73
  • Lastpage
    82
  • Abstract
    The multi-core processors are being widely exploited by many high-end systems and leveraging throughput and scalability. Due to the availability of boosting many concurrent processes, not only the parallel programs but also network server programs can benefit tremendously from multi-core processors. In spite of many researches, modern operating systems still have significant design and optimization space to leverage the network performance over multi-core systems. One of challenging issues is the multi-core aware process scheduling over multiple network interfaces. Multiple network interfaces can provide cost-effective high network bandwidth and high availability. In such systems, it is desirable to adapt the dynamic network loads and manage the system resources efficiently. In this paper, we suggest a novel networking process scheduling scheme called MiAMI for multi-core systems with multiple network interfaces. MiAMI decides an optimal processor affinity based on the processor cache layout, communication intensiveness, and processor loads. The experimental results present that MiAMI implemented in the Linux kernel can improve the effectiveness of processor utilization more than 60% on both Intel SMP and AMD NUMA servers. We also show that, in dynamic application scenarios, MiAMI can improve the network bandwidth and responsiveness more than 30% with less processor resources.
  • Keywords
    Linux; microprocessor chips; network interfaces; network servers; optimisation; transport protocols; AMD NUMA servers; Intel SMP; Linux kernel; MiAMI; TCP/IP; dynamic network; multicore aware processor affinity; multiple network interfaces; network server; optimal processor affinity; optimization; processor cache layout; Availability; Bandwidth; Boosting; Multicore processing; Network interfaces; Network servers; Processor scheduling; Scalability; TCPIP; Throughput; TCP/IP; multi-core; multiple network interfaces; process scheduling; processor affinity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Interconnects, 2009. HOTI 2009. 17th IEEE Symposium on
  • Conference_Location
    New York, NY
  • ISSN
    1550-4794
  • Print_ISBN
    978-0-7695-3847-1
  • Electronic_ISBN
    1550-4794
  • Type

    conf

  • DOI
    10.1109/HOTI.2009.19
  • Filename
    5238682