Title :
Sparse Matrix-Vector Multiplication Design on FPGAs
Author :
Sun, Junqing ; Peterson, Gregory ; Storaasli, Olaf
Author_Institution :
Tennessee Univ., Knoxville
Abstract :
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV solver designed for FPGAs (SSF). Besides high computational throughput, system performance is optimized by reducing initialization time and overheads, minimizing and overlapping I/O operations, and increasing scalability. SSF accepts any matrix size and can be easily adapted to different data formats. SSF minimizes the control logic by taking advantage of the data flow via an innovative accumulation circuit which uses pipelined floating point adders. Compared to optimized software codes on a Pentium 4 microprocessor, our design achieves up to 20x speedup.
Keywords :
field programmable gate arrays; floating point arithmetic; logic design; matrix multiplication; sparse matrices; FPGA; SSF; control logic; data flow; innovative accumulation circuit; pipelined floating point adders; sparse matrix-vector multiplication design; Adders; Design optimization; Field programmable gate arrays; High performance computing; Logic circuits; Microprocessors; Scalability; Sparse matrices; System performance; Throughput; FPGA; Performance; Sparse matrix multiplication;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on
Conference_Location :
Napa, CA
Print_ISBN :
978-0-7695-2940-0
DOI :
10.1109/FCCM.2007.56
