DocumentCode
3345239
Title
Hardware/Software co-design of a key point detector on FPGA
Author
Chati, H. Djakou ; Mühlbauer, F. ; Braun, T. ; Bobda, C. ; Berns, K.
Author_Institution
Kaiserslautern Univ. of Technol., Kaiserslautern
fYear
2007
fDate
23-25 April 2007
Firstpage
355
Lastpage
356
Abstract
The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues.
Keywords
data flow analysis; field programmable gate arrays; hardware-software codesign; FPGA; Xilinx XUP-Virtex II Pro board codesign; data flow management; embedded reconfigurable hardware; field programmable gate array; hardware-software codesign; key point detector algorithm; Change detection algorithms; Convolution; Detectors; Embedded computing; Embedded system; Field programmable gate arrays; Hardware; Object detection; Partitioning algorithms; Robots;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on
Conference_Location
Napa, CA
Print_ISBN
978-0-7695-2940-0
Type
conf
DOI
10.1109/FCCM.2007.61
Filename
4297294
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