A new offset cancellation technique for CMOS differential amplifiers

A new offset cancellation technique for CMOS differential amplifiers is presented where the input offset voltage is reduced by a factor set by the voltage gain in a feedback loop. This approach does not require any active memory or A/D and D/A converters, and can be utilized in the design of operational amplifiers and voltage comparators built in a standard CMOS technology. The input offset voltage is constantly adjusted for improved time and temperature stability. The effect of clock feedthrough voltage on the input offset is reduced by employing a new low frequency clocking scheme with long rise and fall times. Continuous operation is achieved by using a parallel processing configuration where two amplifiers operate sequentially for half of each clock period. Power consumption and die area are considerably lower than any other methods with equivalent performance