Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis

In hard real-time applications, WCET is used to check time constraints of the whole system but is only computed at the task level. While most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware facilities should improve the accuracy of the result. As an example, we developed an analysis of a direct-mapped instruction cache behavior, that combines inter-and intra-task instruction cache analysis to estimate more accurately the number of cache misses due to task chaining by considering task entry and exit states along the inter-task analysis. The initial tasks WCET can be computed by any existing single-task approach that models the instruction cache behavior.