System design using wave-pipelining: a CMOS VLSI vector unit

Wave-pipelining, or maximum rate pipelining, is a circuit design technique which allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques by relying on the predictable finite delay through combinational logic for virtual data storage. Digital system design with ubiquitous use of wave-pipelining faces significant obstacles, including: synthesis and optimization of large wave-pipelined logic structures, synchronization of multiple wave-pipelines with feedback, designing for variation in IC fabrication characteristics, and register and wave-based logic codesign. We have developed analytical models, circuit techniques, and a CMOS wave-pipelining design environment to address these obstacles. These techniques and tools were employed in the design of a CMOS vector processor unit. Wave-pipelining is used in its vector registers and multiplier and adder functional units. This VLSI design is being fabricated in a 1 micron CMOS process and has been simulated at greater than 300 MHz