Title :
Modeling the impact of 3-D-technology on the performance of the memory hierarchy of RISC systems
Author :
Kleiner, Michael B. ; Kühn, Stefan A. ; Weber, Werner
Author_Institution :
Corp. Res. & Dev., Siemens AG, Munich, Germany
fDate :
30 Apr-3 May 1995
Abstract :
In this paper we investigate 3-D-technology for improving the performance of the memory hierarchy of RISC based systems from an architectural point of view. It is assumed that using 3-D-technology, not only the processor and the first-level cache can be integrated onto one IC, but processor, first-level, and second-level cache may be integrated onto one 3-D IC. In addition, the cache may be organized in three levels. Results show, that for a given total cache size the performance in terms of the average time per instruction is improved by 20-35% depending on cache organization
Keywords :
cache storage; integrated circuit modelling; memory architecture; microprocessor chips; reduced instruction set computing; 3D IC technology; RISC systems; cache organization; first-level cache; memory hierarchy; processor integration; second-level cache; three level organization; total cache size; Application software; Degradation; Delay; Integrated circuit modeling; Integrated circuit technology; Random access memory; Reduced instruction set computing; Research and development; Stacking; Three-dimensional integrated circuits;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.523890
