The FPGA implementation of the RC6 and CAST-256 encryption algorithms

The National Institute of Standards and Technology (NIST) in the U.S. has initiated a process to develop an Advanced Encryption Standard (AES) specifying a private-key encryption algorithm based on a 128-bit block size as a replacement for the Data Encryption Standard (DES). We investigate the efficiency of two AES candidates, RC6 and CAST-256, from the hardware implementation perspective with field programmable gate arrays (FPGAs) as the target technology. Our analysis and synthesis studies of the ciphers suggest that it would be desirable for FPGA implementations to have a simpler cipher design that makes use of simpler operations that not only possess good cryptographic properties, but also make the overall cipher design efficient from the hardware implementation perspective.